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H A Dcache.ca4a43fcf9cca1ebd3d26f9a01b923b7393d69c54 Wed Jun 08 05:04:03 UTC 2016 Alexey Brodkin <abrodkin@synopsys.com> arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>