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| H A D | rk3399.dtsi | a34fddcea912a1a6e4b33177aeb0ca3fa1b9a1b4 Mon May 15 06:07:26 UTC 2017 Ziyuan Xu <xzy.xu@rock-chips.com> dts: rk3399: change the maximum eMMC clock frequency to 150MHz
The rockchip mmc controllers don't support _the _odd__ divider,
otherwise probably cause unpredictable error.
The driver originally select gpll(594M) as the clock source, and we set
div to 3 at 200MHz. We have to change the maximum eMMC clock frequency
to 150MHz in U-Boot stage, so that the div will be 4.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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