Searched hist:a21afdff7d01e54f71ec9ff837f6733e48d86b39 (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/include/mm/ |
| H A D | core_mmu.h | a21afdff7d01e54f71ec9ff837f6733e48d86b39 Sun Jun 11 02:13:34 UTC 2023 Alvin Chang <alvinga@andestech.com> core: mm: Introduce next_level field of struct core_mmu_table_info
The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/mm/ |
| H A D | core_mmu.c | a21afdff7d01e54f71ec9ff837f6733e48d86b39 Sun Jun 11 02:13:34 UTC 2023 Alvin Chang <alvinga@andestech.com> core: mm: Introduce next_level field of struct core_mmu_table_info
The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/arm/mm/ |
| H A D | core_mmu_v7.c | a21afdff7d01e54f71ec9ff837f6733e48d86b39 Sun Jun 11 02:13:34 UTC 2023 Alvin Chang <alvinga@andestech.com> core: mm: Introduce next_level field of struct core_mmu_table_info
The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | core_mmu_lpae.c | a21afdff7d01e54f71ec9ff837f6733e48d86b39 Sun Jun 11 02:13:34 UTC 2023 Alvin Chang <alvinga@andestech.com> core: mm: Introduce next_level field of struct core_mmu_table_info
The address translation rule is architecture specific, e.g., ARM adopts
increasing style while the address is translated to finer-grained table,
while RISC-V adopts decreasing style. Therefore, we add a "next_level"
field into the struct core_mmu_table_info, which represents the next
finer-grained translation level. By doing this, we can decouple the
core address translation rule from architecture specific manner.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
|