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Searched hist:"9 d7a059d2ce97cb8e5e9ea7a9d89a34f40e20185" (Results 1 – 3 of 3) sorted by relevance

/rkbin/RKTRUST/
H A DRV1126BTRUST.ini9d7a059d2ce97cb8e5e9ea7a9d89a34f40e20185 Fri Jun 06 07:30:01 UTC 2025 XiaoDong Huang <derrick.huang@rock-chips.com> rv1126b: bl31: update version to v1.06

Build from ATF commit:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
update feature:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
01c91cc55 plat: rv1126b: optimize the speed of system suspend/resume

Change-Id: Ia91db3f2278d0b9afe58550df4b8e34bcffbdea0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
/rkbin/doc/release/
H A DRV1126B_CN.md9d7a059d2ce97cb8e5e9ea7a9d89a34f40e20185 Fri Jun 06 07:30:01 UTC 2025 XiaoDong Huang <derrick.huang@rock-chips.com> rv1126b: bl31: update version to v1.06

Build from ATF commit:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
update feature:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
01c91cc55 plat: rv1126b: optimize the speed of system suspend/resume

Change-Id: Ia91db3f2278d0b9afe58550df4b8e34bcffbdea0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
H A DRV1126B_EN.md9d7a059d2ce97cb8e5e9ea7a9d89a34f40e20185 Fri Jun 06 07:30:01 UTC 2025 XiaoDong Huang <derrick.huang@rock-chips.com> rv1126b: bl31: update version to v1.06

Build from ATF commit:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
update feature:
1b7f2f7db plat: rv1126b: sleep: Set DDR4 CA to high-z
01c91cc55 plat: rv1126b: optimize the speed of system suspend/resume

Change-Id: Ia91db3f2278d0b9afe58550df4b8e34bcffbdea0
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>