| /rk3399_rockchip-uboot/drivers/ram/rockchip/sdram_inc/rv1126/ |
| H A D | sdram-rv1126-ddr3-detect-664.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
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| H A D | sdram-rv1126-ddr3-detect-528.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram-rv1126-ddr3-detect-924.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram-rv1126-ddr3-detect-396.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram-rv1126-ddr3-detect-784.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram-rv1126-ddr3-detect-1056.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram-rv1126-ddr3-detect-328.inc | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| /rk3399_rockchip-uboot/drivers/ram/rockchip/ |
| H A D | sdram_common.c | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|
| H A D | sdram_rv1126.c | 9d5c314b35defd1c678227deba13c3b4dfd4a0f3 Sun Apr 25 07:59:38 UTC 2021 Wesley Yao <wesley.yao@rock-chips.com> drivers: ram: rv1126: Support RV1126 DDR3 x8 bus width
sdram_rv1126.c: 22-28 added to ddrconfig calculate.
sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4
when x8 bus width
sdram_rv1126.c: When detecting DDR3 capacity, the initial value of bus
width is set to 8. Add detection of x8 bus width through read gate
training
sdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8
sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
|