Searched hist:"9 bb367a590feac21d674e4d2cee77702d4774819" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/armv8/ |
| H A D | mmu.h | 9bb367a590feac21d674e4d2cee77702d4774819 Fri Mar 04 00:09:46 UTC 2016 Alexander Graf <agraf@suse.de> arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/ |
| H A D | cache_v8.c | 9bb367a590feac21d674e4d2cee77702d4774819 Fri Mar 04 00:09:46 UTC 2016 Alexander Graf <agraf@suse.de> arm64: Disable TTBR1 maps in EL1
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|