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/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h9978a3fd8b97f024a28be798494b608f43ef5e79 Wed Sep 25 05:56:38 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>