Searched hist:"97405 d843ece2a53e67b801e02ee42005d26e172" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap4/ |
| H A D | clock.h | 97405d843ece2a53e67b801e02ee42005d26e172 Thu May 30 03:19:38 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-omap5/ |
| H A D | clock.h | 97405d843ece2a53e67b801e02ee42005d26e172 Thu May 30 03:19:38 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
|
| /rk3399_rockchip-uboot/include/configs/ |
| H A D | dra7xx_evm.h | 97405d843ece2a53e67b801e02ee42005d26e172 Thu May 30 03:19:38 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | omap_common.h | 97405d843ece2a53e67b801e02ee42005d26e172 Thu May 30 03:19:38 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: DRA7xx: clocks: Update PLL values
Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
|