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| /optee_os/core/arch/riscv/kernel/ |
| H A D | sub.mk | 93e54a63925fd5a785bb13a4cc3a9acbd0f1d2c6 Tue Dec 20 16:47:09 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> riscv: kernel: entry.S: provide entry script
Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread pointer (to thread_core_local), supervisor address
translation and protection register, clearing BSS...etc and calls to
appropriate functions to initialize the MMU and continue to boot flow
from boot.c.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| H A D | entry.S | 93e54a63925fd5a785bb13a4cc3a9acbd0f1d2c6 Tue Dec 20 16:47:09 UTC 2022 Marouene Boubakri <marouene.boubakri@nxp.com> riscv: kernel: entry.S: provide entry script
Provide core's single entry point for RV32/RV64 in S/M Modes.
For now it performs: booting primary and secondary harts. Setting stack
pointer, thread pointer (to thread_core_local), supervisor address
translation and protection register, clearing BSS...etc and calls to
appropriate functions to initialize the MMU and continue to boot flow
from boot.c.
Signed-off-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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