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/rk3399_rockchip-uboot/drivers/ddr/fsl/
H A Dctrl_regs.c938bbb6013f051808c08204184e94d0cdcb6dbff Tue Dec 02 19:18:09 UTC 2014 York Sun <yorksun@freescale.com> driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>