Searched hist:"9127041 a4ce1db729e6024f82229be1ee0520164" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | plat_topology.c | 9127041a4ce1db729e6024f82229be1ee0520164 Fri Jul 25 06:37:45 UTC 2025 Prasad Kummari <prasad.kummari@amd.com> fix(versal-net): move plat_core_pos_by_mpidr to asm
In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() from plat_my_core_pos() results in the
return address stored in register x30 becoming invalid and register
x9 (used later) ends up with the value 0x0. Consequently, the CPU
branches to address 0x0, triggering a synchronous exception. TF-A
then invokes the BHB flush code before resuming execution. However,
since the stack is not properly initialized at this stage, the system
eventually enters plat_panic_handler(). In the updated implementation,
the platform_get_core_pos() function is redefined in assembly to
provide tighter control during early boot stages. The MPIDR_EL1
register contains three affinity levels: Aff0 (bits [0:7]), Aff1
(bits [8:15]), and Aff2 (bits [16:23]). In this assembly function,
the core ID is extracted from Aff1 (MPIDR_AFF1_SHIFT), and the cluster
ID from Aff2 (MPIDR_AFF2_SHIFT). The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.
Change-Id: I090ea107c27dfa643431a97d15556c98f721b2e4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
|
| /rk3399_ARM-atf/plat/xilinx/versal_net/aarch64/ |
| H A D | versal_net_helpers.S | 9127041a4ce1db729e6024f82229be1ee0520164 Fri Jul 25 06:37:45 UTC 2025 Prasad Kummari <prasad.kummari@amd.com> fix(versal-net): move plat_core_pos_by_mpidr to asm
In the current implementation, plat_core_pos_by_mpidr() is defined
in C. When BL31 is compiled with Armclang, a call to
plat_core_pos_by_mpidr() from plat_my_core_pos() results in the
return address stored in register x30 becoming invalid and register
x9 (used later) ends up with the value 0x0. Consequently, the CPU
branches to address 0x0, triggering a synchronous exception. TF-A
then invokes the BHB flush code before resuming execution. However,
since the stack is not properly initialized at this stage, the system
eventually enters plat_panic_handler(). In the updated implementation,
the platform_get_core_pos() function is redefined in assembly to
provide tighter control during early boot stages. The MPIDR_EL1
register contains three affinity levels: Aff0 (bits [0:7]), Aff1
(bits [8:15]), and Aff2 (bits [16:23]). In this assembly function,
the core ID is extracted from Aff1 (MPIDR_AFF1_SHIFT), and the cluster
ID from Aff2 (MPIDR_AFF2_SHIFT). The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.
Change-Id: I090ea107c27dfa643431a97d15556c98f721b2e4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
|