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H A Dsequencer.c8e9e62c946e295ca8e0b81d07b6b1cc884a70bc1 Mon Apr 04 15:28:16 UTC 2016 Marek Vasut <marex@denx.de> ddr: altera: Fix scc_mgr_set() argument order

The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>