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/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_emac.c8e59b9f42374aaa641409b6469c8fe9245a33107 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe
H A Dsocfpga_mailbox.c8e59b9f42374aaa641409b6469c8fe9245a33107 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_mailbox.h8e59b9f42374aaa641409b6469c8fe9245a33107 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.c8e59b9f42374aaa641409b6469c8fe9245a33107 Wed May 17 04:26:11 UTC 2023 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): mailbox and SMC support for Agilex5 SoC FPGA

This patch is used to enable mailbox and SMC support
for Agilex5 SoC FPGA.
1. Enabled mailbox and SMC support.
2. Updated product name -> Agilex5
3. Updated register address based on y22ww52.2 RTL
4. Updated TSN register base address

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I152bee5668b96ef599ded09945167f27a71f23fe