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| H A D | sunxi_mmc.c | 8a647fc3ca2a93e2b6c965999ac2e0316191a755 Thu Aug 31 13:57:48 UTC 2017 Chen-Yu Tsai <wens@csie.org> mmc: sunxi: Only update timing mode bit when enabling new timing mode
When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.
Fixes: de9b1771c3b6 ("mmc: sunxi: Support new mode")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
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