Searched hist:"883402 f5929e1a500e28af53a71d59b60859f4a4" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/riscv/plat-virt/ |
| H A D | conf.mk | 883402f5929e1a500e28af53a71d59b60859f4a4 Sun Apr 28 11:20:33 UTC 2024 Yu Chien Peter Lin <peterlin@andestech.com> core: riscv: use configuration options for RISC-V extensions
RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".
Also, enable RVC and FPU extension for QEMU virt machine.
Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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| /optee_os/core/arch/riscv/ |
| H A D | riscv.mk | 883402f5929e1a500e28af53a71d59b60859f4a4 Sun Apr 28 11:20:33 UTC 2024 Yu Chien Peter Lin <peterlin@andestech.com> core: riscv: use configuration options for RISC-V extensions
RISC-V is a modular ISA, add config options to allow platforms
to customize their binaries with specific "-march" and "-mabi".
Also, enable RVC and FPU extension for QEMU virt machine.
Note that the RISC-V FPU for OP-TEE will be introduced later.
Enable FPU to temporarily bypass incompatible soft/hard-fp
linker errors.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
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