Searched hist:"8755 d50706742e4d302a335f4e69dd6430ec12a2" (Results 1 – 1 of 1) sorted by relevance
| /rk3399_rockchip-uboot/arch/mips/lib/ |
| H A D | cache_init.S | 8755d50706742e4d302a335f4e69dd6430ec12a2 Thu Jan 29 01:28:03 UTC 2015 Paul Burton <paul.burton@imgtec.com> MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
|