Searched hist:"861 ac52a7e80c0399b6e543e7125a9c1e18a63f8" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/include/drivers/ti/uart/ |
| H A D | uart_16550.h | 861ac52a7e80c0399b6e543e7125a9c1e18a63f8 Tue Jan 10 15:34:07 UTC 2017 Nishanth Menon <nm@ti.com> uart: 16550: Fix getc
tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.
Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.
Update the same to match the specification.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
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| /rk3399_ARM-atf/drivers/ti/uart/aarch64/ |
| H A D | 16550_console.S | 861ac52a7e80c0399b6e543e7125a9c1e18a63f8 Tue Jan 10 15:34:07 UTC 2017 Nishanth Menon <nm@ti.com> uart: 16550: Fix getc
tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.
Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.
Update the same to match the specification.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
|