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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ |
| H A D | start.S | 817007c14301d926fa6ec83a37271b6848cca145 Tue Jan 02 11:05:07 UTC 2018 Joseph Chen <chenjh@rock-chips.com> armv7: start.S: enable ACTLR.SMP bit
For cortex-A7 core, when ACTLR.SMP is 0 during the processor
power-up and power-down procedures, the caches are disabled
regardless of the SCTLR.C bit setting. It's similar for other
cortex A series core.
Change-Id: I69512787015d651fe5bb5d6961f5ed01c2505058
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
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