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/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dsocfpga_plat_def.h7c72dfac962ce1e1f95be4c974b691d667a8eae4 Thu Apr 04 03:16:09 UTC 2024 Jit Loon Lim <jit.loon.lim@intel.com> fix(intel): update sip smc config addr for agilex5

Agilex5 DDR base address started from 0x8000 0000.
Thus the SIP_SMC_FPGA_CONFIG_ADDR shall be offset to
0x8040 0000.

Change-Id: I33a840cb8ebbe02bc7ff9b1f5d452641af11e576
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>