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| H A D | tc_helpers.S | 7b41acaf72dc208601c315189756fdb9f24f4abf Fri Jul 05 11:15:15 UTC 2024 Jagdish Gediya <jagdish.gediya@arm.com> fix(tc): enable Last-level cache (LLC) for tc4
EXTLLC bit in CPUECTLR_EL1(for non-gelas cpus) and in CPUECTLR2_EL1
register for gelas cpu enables external Last-level cache in the system,
External LLC is present on TC4 systems in MCN but it is not enabled in
CPU registers so enable it.
On TC4, Gelas vs Non-Gelas CPUs have different bits to enable EXTLLC
so take care of that as well.
Change-Id: Ic6a74b4af110a3c34d19131676e51901ea2bf6e3
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
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