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| H A D | mp.c | 7afc45ad7d9493208d89072cbb78a5bfc8034b59 Sun Mar 13 15:55:53 UTC 2011 Kumar Gala <galak@kernel.crashing.org> powerpc/85xx: Fix synchronization of timebase on MP boot
There is a small ordering issue in the master core in that we need to
make sure the disabling of the timebase in the SoC is visible before we
set the value to 0. We can simply just read back the value to
synchronizatize the write, before we set TB to 0.
Reported-by: Dan Hettena
Tested-by: Dan Hettena
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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