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| /optee_os/core/arch/arm/kernel/ |
| H A D | thread_a32.S | 79454c60da6ac9ed6914c28ce3d984a3cfa847d9 Tue Feb 04 16:30:55 UTC 2020 Jens Wiklander <jens.wiklander@linaro.org> core: add thread_smccc()
Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first 8 registers is then saved in
the argument struct.
With the new flag CFG_CORE_SEL2_SPMC configures OP-TEE to work with a
SPMC at S-EL2 instead of the dispatcher at EL3. The SMC instruction
should not be used when working with a SPMC, OP-TEE should instead use
the HVC instruction in such a configuration.
Without a SPMC at S-EL2 OP-TEE works with the dispatcher at EL3 with no
changes.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| H A D | thread_a64.S | 79454c60da6ac9ed6914c28ce3d984a3cfa847d9 Tue Feb 04 16:30:55 UTC 2020 Jens Wiklander <jens.wiklander@linaro.org> core: add thread_smccc()
Adds the assembly function thread_smccc() which loads the first 8
registers with the argument and executes an SMC or HVC instruction as
appropriate. The result in the first 8 registers is then saved in
the argument struct.
With the new flag CFG_CORE_SEL2_SPMC configures OP-TEE to work with a
SPMC at S-EL2 instead of the dispatcher at EL3. The SMC instruction
should not be used when working with a SPMC, OP-TEE should instead use
the HVC instruction in such a configuration.
Without a SPMC at S-EL2 OP-TEE works with the dispatcher at EL3 with no
changes.
Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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