Searched hist:"78 e2bd10aed75e2dd7d47abefd6270935fb889b7" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_fiq_glue.c | 78e2bd10aed75e2dd7d47abefd6270935fb889b7 Tue Dec 29 00:36:42 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra: implement FIQ interrupt handler
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | tegra_sip_calls.c | 78e2bd10aed75e2dd7d47abefd6270935fb889b7 Tue Dec 29 00:36:42 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra: implement FIQ interrupt handler
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | tegra_common.mk | 78e2bd10aed75e2dd7d47abefd6270935fb889b7 Tue Dec 29 00:36:42 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra: implement FIQ interrupt handler
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/include/ |
| H A D | tegra_private.h | 78e2bd10aed75e2dd7d47abefd6270935fb889b7 Tue Dec 29 00:36:42 UTC 2015 Varun Wadekar <vwadekar@nvidia.com> Tegra: implement FIQ interrupt handler
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Change-Id: I733af61a08d1318c75acedbe9569a758744edd0c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|