Searched hist:"71214 c120244916358a53e1662b4807f103eb941" (Results 1 – 3 of 3) sorted by relevance
| /optee_os/core/arch/riscv/include/mm/ |
| H A D | core_mmu_arch.h | 71214c120244916358a53e1662b4807f103eb941 Fri Apr 11 06:18:52 UTC 2025 Alvin Chang <alvinga@andestech.com> riscv: mm: support Sv48 and Sv57 address translation for core and TA
Add the macros for Sv57 address translation mode. Add CFG_RISCV_MMU_MODE
into riscv.mk and set it as 39 by default to enable Sv39 virtual address
translation scheme.
Currently, TA virtual memory occupies 1GB space, and TAs page table
should be an entry inside a level 2 (VPN[2]) page table, which is
decided by user_va_idx variable. For Sv39 translation scheme, it starts
from VPN[2], so nothing to do. For Sv48 translation scheme, we need to
allocate entry 0 of level 3 (VPN[3]) page table, and let it point to the
level 2 page table used by TA. For Sv57 translation scheme, we need to
further allocate entry 0 of level 4 (VPN[4]) page table, and let it
point to the level 3 page table.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/riscv/ |
| H A D | riscv.mk | 71214c120244916358a53e1662b4807f103eb941 Fri Apr 11 06:18:52 UTC 2025 Alvin Chang <alvinga@andestech.com> riscv: mm: support Sv48 and Sv57 address translation for core and TA
Add the macros for Sv57 address translation mode. Add CFG_RISCV_MMU_MODE
into riscv.mk and set it as 39 by default to enable Sv39 virtual address
translation scheme.
Currently, TA virtual memory occupies 1GB space, and TAs page table
should be an entry inside a level 2 (VPN[2]) page table, which is
decided by user_va_idx variable. For Sv39 translation scheme, it starts
from VPN[2], so nothing to do. For Sv48 translation scheme, we need to
allocate entry 0 of level 3 (VPN[3]) page table, and let it point to the
level 2 page table used by TA. For Sv57 translation scheme, we need to
further allocate entry 0 of level 4 (VPN[4]) page table, and let it
point to the level 3 page table.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|
| /optee_os/core/arch/riscv/mm/ |
| H A D | core_mmu_arch.c | 71214c120244916358a53e1662b4807f103eb941 Fri Apr 11 06:18:52 UTC 2025 Alvin Chang <alvinga@andestech.com> riscv: mm: support Sv48 and Sv57 address translation for core and TA
Add the macros for Sv57 address translation mode. Add CFG_RISCV_MMU_MODE
into riscv.mk and set it as 39 by default to enable Sv39 virtual address
translation scheme.
Currently, TA virtual memory occupies 1GB space, and TAs page table
should be an entry inside a level 2 (VPN[2]) page table, which is
decided by user_va_idx variable. For Sv39 translation scheme, it starts
from VPN[2], so nothing to do. For Sv48 translation scheme, we need to
allocate entry 0 of level 3 (VPN[3]) page table, and let it point to the
level 2 page table used by TA. For Sv57 translation scheme, we need to
further allocate entry 0 of level 4 (VPN[4]) page table, and let it
point to the level 3 page table.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
|