Searched hist:"7096 d2bca0308f3b9539532f552994b09455fb29" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a65ae.S | 7096d2bca0308f3b9539532f552994b09455fb29 Wed Jan 28 15:24:00 UTC 2026 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65AE erratum 1638571
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/getting_started/ |
| H A D | build-options.rst | 7096d2bca0308f3b9539532f552994b09455fb29 Wed Jan 28 15:24:00 UTC 2026 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65AE erratum 1638571
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 7096d2bca0308f3b9539532f552994b09455fb29 Wed Jan 28 15:24:00 UTC 2026 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65AE erratum 1638571
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 7096d2bca0308f3b9539532f552994b09455fb29 Wed Jan 28 15:24:00 UTC 2026 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65AE erratum 1638571
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|
| /rk3399_ARM-atf/ |
| H A D | Makefile | 7096d2bca0308f3b9539532f552994b09455fb29 Wed Jan 28 15:24:00 UTC 2026 Xialin Liu <xialin.liu@arm.com> fix(cpus): workaround for Cortex-A65AE erratum 1638571
Cortex-A65AE erratum 1638571 is a Cat B erratum that applies
to revisions r0p0, r1p0, r1p1, and is still open.
This erratum can be avoided by disable stage1 page table walk for
lower Els (EL1 and EL0) in EL3, so 'AT' speculative fetch at any
point produces either the correct result or failure without TLB
allocation.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1344564/latest
Change-Id: I861230de94a105fd52f9c8ef7e7551a2633c065b
Signed-off-by: Xialin Liu <xialin.liu@arm.com>
|