Searched hist:"66869 f955417b89dbf6b7cbb72738b2205a26bf8" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/drivers/ddr/fsl/ |
| H A D | interactive.c | 66869f955417b89dbf6b7cbb72738b2205a26bf8 Thu Mar 19 16:30:26 UTC 2015 York Sun <yorksun@freescale.com> drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | util.c | 66869f955417b89dbf6b7cbb72738b2205a26bf8 Thu Mar 19 16:30:26 UTC 2015 York Sun <yorksun@freescale.com> drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | main.c | 66869f955417b89dbf6b7cbb72738b2205a26bf8 Thu Mar 19 16:30:26 UTC 2015 York Sun <yorksun@freescale.com> drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| H A D | ctrl_regs.c | 66869f955417b89dbf6b7cbb72738b2205a26bf8 Thu Mar 19 16:30:26 UTC 2015 York Sun <yorksun@freescale.com> drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
|
| /rk3399_rockchip-uboot/include/ |
| H A D | fsl_ddr.h | 66869f955417b89dbf6b7cbb72738b2205a26bf8 Thu Mar 19 16:30:26 UTC 2015 York Sun <yorksun@freescale.com> drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
Signed-off-by: York Sun <yorksun@freescale.com>
|