Searched hist:"61923 c833530bb097aa424f00eaffdba7873eb89" (Results 1 – 2 of 2) sorted by relevance
| /rkbin/RKTRUST/ |
| H A D | RK3358TRUST.ini | 61923c833530bb097aa424f00eaffdba7873eb89 Fri Feb 18 10:01:13 UTC 2022 Zhihuan He <huan.he@rock-chips.com> rk3326: bl31: update version to v1.27
Build from ATF commit:
96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
96550638e plat: px30-s: dram: phy io ctrl save and resume
16b51a9f9 plat: px30-s: dram: fix ck/ckb to low before deepsleep
90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
c5157a42e plat: px30-s: Restore DDR PHY dfi low power function
0de2c3db8 plat: px30: sleep: enter ddr sref by software
16fda9dd6 plat: px30s: suspend: add ddr resume support
91188bd6f plat: px30: suspend: support ddr resume
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I5cc4bf115cc194a6c6c21ea452031d0898fe1b97
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| H A D | RK3326TRUST.ini | 61923c833530bb097aa424f00eaffdba7873eb89 Fri Feb 18 10:01:13 UTC 2022 Zhihuan He <huan.he@rock-chips.com> rk3326: bl31: update version to v1.27
Build from ATF commit:
96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
96550638e plat: px30-s: dram: phy io ctrl save and resume
16b51a9f9 plat: px30-s: dram: fix ck/ckb to low before deepsleep
90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
c5157a42e plat: px30-s: Restore DDR PHY dfi low power function
0de2c3db8 plat: px30: sleep: enter ddr sref by software
16fda9dd6 plat: px30s: suspend: add ddr resume support
91188bd6f plat: px30: suspend: support ddr resume
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I5cc4bf115cc194a6c6c21ea452031d0898fe1b97
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