Searched hist:"5 fbf4949b1a796614051e716dbccac6f4a44a401" (Results 1 – 8 of 8) sorted by relevance
| /rkbin/RKBOOT/ |
| H A D | RV1106MINIALL_EMMC_TB_NOMCU.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
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| H A D | RV1106MINIALL_SPI_NOR_TB_NOMCU.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| H A D | RV1106MINIALL_SPI_NOR_TB.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| H A D | RV1106MINIALL_SPI_NOR_TB_GC2093.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| H A D | RV1106MINIALL_EMMC_TB.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| H A D | RV1106MINIALL.ini | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| /rkbin/doc/release/ |
| H A D | RV1106_EN.md | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|
| H A D | RV1106_CN.md | 5fbf4949b1a796614051e716dbccac6f4a44a401 Fri Nov 11 10:10:58 UTC 2022 Wesley Yao <wesley.yao@rock-chips.com> rv1106: ddr: Update DDR bin to v1.10 20221115
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
|