Searched hist:"5 fb0151697088e257e0190d414cc7b2e2793b485" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/x86/dts/ |
| H A D | bayleybay.dts | 5fb0151697088e257e0190d414cc7b2e2793b485 Sat Aug 15 20:37:50 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| H A D | minnowmax.dts | 5fb0151697088e257e0190d414cc7b2e2793b485 Sat Aug 15 20:37:50 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: baytrail: Support multiple microcode copies
Intel FSP has the capability to walk through the microcode blocks
which are passed as the TempRamInit() parameter from U-Boot and
finds the most appropriate microcode which is suitable for the cpu
on which it is running. Now we've seen several steppings for Intel
BayTrail series processors, adding those microcodes to the Intel
BayleyBay and MinnowMax board device tree files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
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