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H A Dentry.S5ee429d5b99102a643164b86bbd0c3c81735c402 Sun Jun 22 17:03:41 UTC 2025 Yu-Chien Peter Lin <peter.lin@sifive.com> core: riscv: fix hartid at secondary hart entry point

The a0 register is corrupted during enable_mmu, so get
secondary hartid from s0 instead.

Fixes: 29661368f51d ("core: riscv: preserve hartid in s0 register at entry point")
Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>