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/rk3399_rockchip-uboot/include/configs/
H A DT1040QDS.h562de1d6da5bdc1789bd258d464d6ca57571861d Thu Dec 12 06:39:01 UTC 2013 Prabhakar Kushwaha <prabhakar@freescale.com> board/t1040qds: Relax IFC FPGA timings

Current IFC-FPGA TCH(Chip Select hold time with respect to WE deassertion)
is 0 i.e. 0 ns hold time on writes. This may not work on higher clock
freqencies.

So, Increase TCH as 0x8 i.e. 8 ip_clk.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>