Searched hist:"53 a868f676d9ad6ec37d69155241883b8e7bf0bf" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/ti/k3/include/ |
| H A D | platform_def.h | 53a868f676d9ad6ec37d69155241883b8e7bf0bf Wed Oct 25 21:42:27 UTC 2023 Andrew Davis <afd@ti.com> fix(ti): align static device region addresses to reduce MMU table count
Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a single entry in the
higher order table, vs having to create a new table for LV3 entries.
This reduces our tables to just 4: 2 LV2 and 1 LV3 plus 1 spare in case
alignment changes ever cause one to be split. This saves 24KB of our
128KB total TF-A SRAM (~18%!).
While here, as USE_COHERENT_MEM does not change MAX_XLAT_TABLES but
does change our total MAX_MMAP_REGIONS, move that check accordingly.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I4cb8e3b2cc3d05c6c9a84d887dd6ec56bde7a786
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| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_bl31_setup.c | 53a868f676d9ad6ec37d69155241883b8e7bf0bf Wed Oct 25 21:42:27 UTC 2023 Andrew Davis <afd@ti.com> fix(ti): align static device region addresses to reduce MMU table count
Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a single entry in the
higher order table, vs having to create a new table for LV3 entries.
This reduces our tables to just 4: 2 LV2 and 1 LV3 plus 1 spare in case
alignment changes ever cause one to be split. This saves 24KB of our
128KB total TF-A SRAM (~18%!).
While here, as USE_COHERENT_MEM does not change MAX_XLAT_TABLES but
does change our total MAX_MMAP_REGIONS, move that check accordingly.
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I4cb8e3b2cc3d05c6c9a84d887dd6ec56bde7a786
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