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| H A D | riscv.mk | 51b745fab86c61f211c04c8e6fc3edcf346b01c9 Sat Mar 02 09:16:35 UTC 2024 Etienne Carriere <etienne.carriere@foss.st.com> core: riscv: force enable of CFG_CORE_HAS_GENERIC_TIMER
Ensure CFG_CORE_HAS_GENERIC_TIMER is enabled for RISC-V architecture
since the current implementation provides the necessary routines
in delay_arch.h outside any configuration switch directive. This change
clarifies riscv based platforms configuration that previously depended
on CFG_CORE_HAS_GENERIC_TIMER default enabling from mk/config.mk.
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
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