Searched hist:"4 c4387dc246eba2f29069c8e59ecffebde88aae7" (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/arch/riscv/include/mm/ |
| H A D | core_mmu_arch.h | 4c4387dc246eba2f29069c8e59ecffebde88aae7 Mon Feb 26 02:20:22 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Prepare SATP for each hart
To support multiple harts environment, we have allocated root page table
for each hart. Further more, we need to prepare value of CSR SATP, which
holds the physical page number (PPN) of the root page table, for each
hart.
This commit enlarges the "struct core_mmu_config" for RISC-V
architecture to hold the value of CSR SATP for all the harts. In early
boot stage, each hart should initialize its CSR SATP from "struct
core_mmu_config".
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/arch/riscv/kernel/ |
| H A D | asm-defines.c | 4c4387dc246eba2f29069c8e59ecffebde88aae7 Mon Feb 26 02:20:22 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Prepare SATP for each hart
To support multiple harts environment, we have allocated root page table
for each hart. Further more, we need to prepare value of CSR SATP, which
holds the physical page number (PPN) of the root page table, for each
hart.
This commit enlarges the "struct core_mmu_config" for RISC-V
architecture to hold the value of CSR SATP for all the harts. In early
boot stage, each hart should initialize its CSR SATP from "struct
core_mmu_config".
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| H A D | entry.S | 4c4387dc246eba2f29069c8e59ecffebde88aae7 Mon Feb 26 02:20:22 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Prepare SATP for each hart
To support multiple harts environment, we have allocated root page table
for each hart. Further more, we need to prepare value of CSR SATP, which
holds the physical page number (PPN) of the root page table, for each
hart.
This commit enlarges the "struct core_mmu_config" for RISC-V
architecture to hold the value of CSR SATP for all the harts. In early
boot stage, each hart should initialize its CSR SATP from "struct
core_mmu_config".
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|
| /optee_os/core/arch/riscv/mm/ |
| H A D | core_mmu_arch.c | 4c4387dc246eba2f29069c8e59ecffebde88aae7 Mon Feb 26 02:20:22 UTC 2024 Alvin Chang <alvinga@andestech.com> core: riscv: Prepare SATP for each hart
To support multiple harts environment, we have allocated root page table
for each hart. Further more, we need to prepare value of CSR SATP, which
holds the physical page number (PPN) of the root page table, for each
hart.
This commit enlarges the "struct core_mmu_config" for RISC-V
architecture to hold the value of CSR SATP for all the harts. In early
boot stage, each hart should initialize its CSR SATP from "struct
core_mmu_config".
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Marouene Boubakri <marouene.boubakri@nxp.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
|