Searched hist:"4 baa0ab67d504f3b4318f999631e3f83d0c52c4a" (Results 1 – 6 of 6) sorted by relevance
| /rk3399_rockchip-uboot/arch/mips/include/asm/ |
| H A D | cm.h | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| H A D | mipsregs.h | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| H A D | global_data.h | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| /rk3399_rockchip-uboot/arch/mips/lib/ |
| H A D | cache.c | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| H A D | cache_init.S | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| /rk3399_rockchip-uboot/arch/mips/ |
| H A D | Kconfig | 4baa0ab67d504f3b4318f999631e3f83d0c52c4a Wed Sep 21 10:18:54 UTC 2016 Paul Burton <paul.burton@imgtec.com> MIPS: L2 cache support
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early in boot & initialise
the L1 caches first, such that we can start making use of the L1
instruction cache as early as possible. Otherwise we initialise the L2
first such that the L1s have no opportunity to generate access to the
uninitialised L2.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|