Searched hist:"4 acd900df6275cd724266157e04e2b75d82cf24a" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gicv2.h | 4acd900df6275cd724266157e04e2b75d82cf24a Wed Mar 21 08:55:47 UTC 2018 Marcin Wojtas <mw@semihalf.com> gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.
Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| /rk3399_ARM-atf/drivers/arm/gic/v2/ |
| H A D | gicv2_main.c | 4acd900df6275cd724266157e04e2b75d82cf24a Wed Mar 21 08:55:47 UTC 2018 Marcin Wojtas <mw@semihalf.com> gicv2: enable configuring IRQ trigger type
This patch introduces new helper routines that allow
configuring the individual IRQs to be edge/level-triggered
via GICD_ICFGR registers. This is helpful to modify
the default configuration of the non-secure GIC SPI's, which
are all set during initialization to be level-sensitive.
Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
|