Searched hist:"3 aaf25d23564797e57fc3bd8e8a2fbb9e0dacb71" (Results 1 – 4 of 4) sorted by relevance
| /optee_os/core/include/mm/ |
| H A D | core_mmu.h | 3aaf25d23564797e57fc3bd8e8a2fbb9e0dacb71 Thu Mar 10 17:14:34 UTC 2022 Etienne Carriere <etienne.carriere@linaro.org> core: mm: fix core virtual address range constraint in lpae
Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.
Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| /optee_os/core/mm/ |
| H A D | core_mmu.c | 3aaf25d23564797e57fc3bd8e8a2fbb9e0dacb71 Thu Mar 10 17:14:34 UTC 2022 Etienne Carriere <etienne.carriere@linaro.org> core: mm: fix core virtual address range constraint in lpae
Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.
Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| /optee_os/core/arch/arm/mm/ |
| H A D | core_mmu_v7.c | 3aaf25d23564797e57fc3bd8e8a2fbb9e0dacb71 Thu Mar 10 17:14:34 UTC 2022 Etienne Carriere <etienne.carriere@linaro.org> core: mm: fix core virtual address range constraint in lpae
Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.
Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
|
| H A D | core_mmu_lpae.c | 3aaf25d23564797e57fc3bd8e8a2fbb9e0dacb71 Thu Mar 10 17:14:34 UTC 2022 Etienne Carriere <etienne.carriere@linaro.org> core: mm: fix core virtual address range constraint in lpae
Changes strategy to set core virtual memory addresses in case pager
is enabled (CFG_WITH_PAGER=y) with LPAE (CFG_WITH_LPAE=y). In this
configuration the virtual memory addresses are expected to fit in a
single base translation table in order to save 4kB translation pages.
This change makes core to fallback to the generic layout, possibly
spreading virtual addresses over several base translation tables if
the virtual memory addresses do not fit in the optimized address
range preferred for that configuration.
Fixes: https://github.com/OP-TEE/optee_os/issues/5201
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
|