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/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_pinmux.h3905f57134853f47f6e859b8b6322a7dbbfc49f7 Wed Jun 15 12:59:33 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): setup FPGA interface for Agilex

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_pinmux.c3905f57134853f47f6e859b8b6322a7dbbfc49f7 Wed Jun 15 12:59:33 UTC 2022 Jit Loon Lim <jit.loon.lim@intel.com> feat(intel): setup FPGA interface for Agilex

Enable/Disable FPGA interfaces based on handoff configuration.

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5