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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | asm_macros.S | 387b8801f956204b2970a5b65de0f9ad6821a4b7 Fri Nov 25 14:10:13 UTC 2022 Andre Przywara <andre.przywara@arm.com> refactor(cpufeat): use alternative encoding for "SB" barrier
The "sb" barrier instruction is a rather new addition to the AArch64
instruction set, so it is not recognised by all toolchains. On top of
that, the GNU assembler denies this instruction, unless a compatible
processor is selected:
asm_macros.S:223: Error: selected processor does not support `sb'
Provide an alternative encoding of the "sb" instruction, by using a
system register write, as this is the group where the barrier
instructions borrow their encoding space from.
This results in the exact same opcode to be generated, and any
disassembler will decode this instruction as "sb".
Change-Id: I5f44c8321e0cc04c784e02bd838e964602a96a8e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| H A D | arch.h | 387b8801f956204b2970a5b65de0f9ad6821a4b7 Fri Nov 25 14:10:13 UTC 2022 Andre Przywara <andre.przywara@arm.com> refactor(cpufeat): use alternative encoding for "SB" barrier
The "sb" barrier instruction is a rather new addition to the AArch64
instruction set, so it is not recognised by all toolchains. On top of
that, the GNU assembler denies this instruction, unless a compatible
processor is selected:
asm_macros.S:223: Error: selected processor does not support `sb'
Provide an alternative encoding of the "sb" instruction, by using a
system register write, as this is the group where the barrier
instructions borrow their encoding space from.
This results in the exact same opcode to be generated, and any
disassembler will decode this instruction as "sb".
Change-Id: I5f44c8321e0cc04c784e02bd838e964602a96a8e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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