Searched hist:"37 f760241e75bbfa5c4043f9e451fc0ce7ed42f7" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/ |
| H A D | plat_psci_handlers.c | 37f760241e75bbfa5c4043f9e451fc0ce7ed42f7 Mon Apr 09 22:18:02 UTC 2018 kalyani chidambaram <kalyanic@nvidia.com> Tegra210: secure PMC hardware block
This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.
The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.
Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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| H A D | plat_setup.c | 37f760241e75bbfa5c4043f9e451fc0ce7ed42f7 Mon Apr 09 22:18:02 UTC 2018 kalyani chidambaram <kalyanic@nvidia.com> Tegra210: secure PMC hardware block
This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.
The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.
Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
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