Searched hist:"33 fb6c0100de6dbc79d0237418941cc40e94b16d" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_rockchip-uboot/arch/x86/dts/microcode/ |
| H A D | m12306a8_00000010.dtsi | 33fb6c0100de6dbc79d0237418941cc40e94b16d Fri Dec 11 10:55:47 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: ivybridge: Add microcode blobs for all the steppings
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
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| H A D | m12306a5_00000007.dtsi | 33fb6c0100de6dbc79d0237418941cc40e94b16d Fri Dec 11 10:55:47 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: ivybridge: Add microcode blobs for all the steppings
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
| H A D | m12306a4_00000007.dtsi | 33fb6c0100de6dbc79d0237418941cc40e94b16d Fri Dec 11 10:55:47 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: ivybridge: Add microcode blobs for all the steppings
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|
| H A D | m12306a2_00000008.dtsi | 33fb6c0100de6dbc79d0237418941cc40e94b16d Fri Dec 11 10:55:47 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: ivybridge: Add microcode blobs for all the steppings
This adds microcode blobs created from Intel FSP package for the
Chief River platform. They are for all the Ivy Bridge steppings:
306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the
306a9 which is already in the U-Boot tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
|