Searched hist:"33 ec1a00a44f7c1dad890dddf46d2dc7faf08a15" (Results 1 – 3 of 3) sorted by relevance
| /rkbin/RKTRUST/ |
| H A D | RK3562TRUST.ini | 33ec1a00a44f7c1dad890dddf46d2dc7faf08a15 Thu Apr 27 02:14:13 UTC 2023 Liang Chen <cl@rock-chips.com> rk3562: bl31: update version to v1.15
build form:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
update feature:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
84db911a8 plat: rk3562: add soc version init
13293ddbe plat: rk3588: hdmirx: reset controller as soon as possible
7595dc437 rockchip: increase FDT buffer size
bbaa2847c plat: rk3528: dmc: suspend: Add pctl and phy reg that need save
d47912428 plat: rk3528: Add support of dmc
398d70f4c plat: rk3528: support stop cpus
85fc734b9 plat: rockchip: rk3588: dmc: update lp5 mr for each channel
aef7950e4 plat: rk_fpga: add rk_fpga_rk3576 support
b56fd461a plat: rk_fpga: define uart macro in each rk_fpga_soc_def.h
8f84fa572 plat: rockchip: fiq: dsb, isb and nop after wfe in cpu_stop_for_event()
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I418b329c89f07423a2185b99bc48fe5e22a70a87
|
| /rkbin/doc/release/ |
| H A D | RK3562_EN.md | 33ec1a00a44f7c1dad890dddf46d2dc7faf08a15 Thu Apr 27 02:14:13 UTC 2023 Liang Chen <cl@rock-chips.com> rk3562: bl31: update version to v1.15
build form:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
update feature:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
84db911a8 plat: rk3562: add soc version init
13293ddbe plat: rk3588: hdmirx: reset controller as soon as possible
7595dc437 rockchip: increase FDT buffer size
bbaa2847c plat: rk3528: dmc: suspend: Add pctl and phy reg that need save
d47912428 plat: rk3528: Add support of dmc
398d70f4c plat: rk3528: support stop cpus
85fc734b9 plat: rockchip: rk3588: dmc: update lp5 mr for each channel
aef7950e4 plat: rk_fpga: add rk_fpga_rk3576 support
b56fd461a plat: rk_fpga: define uart macro in each rk_fpga_soc_def.h
8f84fa572 plat: rockchip: fiq: dsb, isb and nop after wfe in cpu_stop_for_event()
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I418b329c89f07423a2185b99bc48fe5e22a70a87
|
| H A D | RK3562_CN.md | 33ec1a00a44f7c1dad890dddf46d2dc7faf08a15 Thu Apr 27 02:14:13 UTC 2023 Liang Chen <cl@rock-chips.com> rk3562: bl31: update version to v1.15
build form:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
update feature:
904af256f plat: rk3562: clock: adjust pvtpll config for cpu/gpu/npu
84db911a8 plat: rk3562: add soc version init
13293ddbe plat: rk3588: hdmirx: reset controller as soon as possible
7595dc437 rockchip: increase FDT buffer size
bbaa2847c plat: rk3528: dmc: suspend: Add pctl and phy reg that need save
d47912428 plat: rk3528: Add support of dmc
398d70f4c plat: rk3528: support stop cpus
85fc734b9 plat: rockchip: rk3588: dmc: update lp5 mr for each channel
aef7950e4 plat: rk_fpga: add rk_fpga_rk3576 support
b56fd461a plat: rk_fpga: define uart macro in each rk_fpga_soc_def.h
8f84fa572 plat: rockchip: fiq: dsb, isb and nop after wfe in cpu_stop_for_event()
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I418b329c89f07423a2185b99bc48fe5e22a70a87
|