Searched hist:"322 e7c3e003cdcf954fb1e82cb9184405e053d03" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/include/ |
| H A D | platform_def.h | 322e7c3e003cdcf954fb1e82cb9184405e053d03 Mon Apr 10 08:20:32 UTC 2017 Harvey Hsieh <hhsieh@nvidia.com> Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_pm.c | 322e7c3e003cdcf954fb1e82cb9184405e053d03 Mon Apr 10 08:20:32 UTC 2017 Harvey Hsieh <hhsieh@nvidia.com> Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | tegra_bl31_setup.c | 322e7c3e003cdcf954fb1e82cb9184405e053d03 Mon Apr 10 08:20:32 UTC 2017 Harvey Hsieh <hhsieh@nvidia.com> Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|