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| H A D | designware_spi.c | 300e61c1ec1bcf0c06a154514c87b09a2d73f7d4 Thu Apr 19 14:47:41 UTC 2018 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> UPSTREAM: spi: dw: invert wait condition in dw_spi_xfer
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.
Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Change-Id: I741ce99a6b6cf57c248426549c0047d636d9e43e
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9b14ac5cc2294ac3eaae92421abff27ed3e6caae)
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