Searched hist:"2 c95211167091e543e20f4f457d3d1f1f660a6d4" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/board/ti/am43xx/ |
| H A D | board.h | 2c95211167091e543e20f4f457d3d1f1f660a6d4 Fri Jun 27 18:31:14 UTC 2014 Franklin S. Cooper Jr <fcooper@ti.com> am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
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| H A D | board.c | 2c95211167091e543e20f4f457d3d1f1f660a6d4 Fri Jun 27 18:31:14 UTC 2014 Franklin S. Cooper Jr <fcooper@ti.com> am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-am33xx/ |
| H A D | omap.h | 2c95211167091e543e20f4f457d3d1f1f660a6d4 Fri Jun 27 18:31:14 UTC 2014 Franklin S. Cooper Jr <fcooper@ti.com> am43xx: Update EMIF DDR3 Configuration for AM43x GP
* Boot failures have been discovered due to a combination of routing issues and
non optimal ddr3 timings in the EMIF
* Since ddr3 timings are different after significant board layout changes
different timings are required for alpha, beta and production boards.
Signed-off-by: Franklin S. Cooper Jr <fcooper@ti.com>
|