Searched hist:"2 b028a2ba197af1fea5d1c6121a9482174285164" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32-core.h | 2b028a2ba197af1fea5d1c6121a9482174285164 Wed Aug 28 14:10:33 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> clk: implement multi-gate management at core level
The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a counter on the gates.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| H A D | clk-stm32-core.c | 2b028a2ba197af1fea5d1c6121a9482174285164 Wed Aug 28 14:10:33 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> clk: implement multi-gate management at core level
The majority of all peripherals have their bus and kernel clocks with
the same clock gating register bit. Therefore it is mandatory to handle
a counter on the gates.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>
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