Searched hist:"284 b2f095bce33487fd6d3c3c11e77ef8d79dd3f" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/ |
| H A D | pm_api_clock.h | 284b2f095bce33487fd6d3c3c11e77ef8d79dd3f Wed Jan 02 21:45:53 UTC 2019 Jolly Shah <jollys@xilinx.com> zynqmp: pm: Fix model of ACPU clocks
In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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| H A D | pm_api_clock.c | 284b2f095bce33487fd6d3c3c11e77ef8d79dd3f Wed Jan 02 21:45:53 UTC 2019 Jolly Shah <jollys@xilinx.com> zynqmp: pm: Fix model of ACPU clocks
In the existing model for ACPU clock the mux, divider, and gate were
represented as one clock and ACPU_HALF was modelled as child of
ACPU clock. This is not correct. ACPU clock model contains only
mux and the divider, and it has 2 children: ACPU_FULL and ACPU_HALF
clocks which have only gates. The models of ACPU and ACPU_HALF clocks
are fixed and ACPU_FULL clock is added.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
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