Searched hist:"25 a93f7cd181ca79a631864b7c076fa7106f4365" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/bl32/sp_min/aarch32/ |
| H A D | entrypoint.S | 25a93f7cd181ca79a631864b7c076fa7106f4365 Thu Jan 05 10:37:21 UTC 2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com> Enable data caches early with hardware-assisted coherency
At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.
On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.
Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| /rk3399_ARM-atf/bl31/aarch64/ |
| H A D | bl31_entrypoint.S | 25a93f7cd181ca79a631864b7c076fa7106f4365 Thu Jan 05 10:37:21 UTC 2017 Jeenu Viswambharan <jeenu.viswambharan@arm.com> Enable data caches early with hardware-assisted coherency
At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.
On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.
Change-Id: Icb0adb026e01aecf34beadf49c88faa9dd368327
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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