Searched hist:"21 f0fd245e311fdb0d8a79747437595d9fab1536" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/ |
| H A D | Kconfig | 21f0fd245e311fdb0d8a79747437595d9fab1536 Tue Apr 21 05:18:40 UTC 2015 Ian Campbell <ijc@hellion.org.uk> jetson-tk1: Add PSCI configuration options and reserve secure code
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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| /rk3399_rockchip-uboot/include/configs/ |
| H A D | jetson-tk1.h | 21f0fd245e311fdb0d8a79747437595d9fab1536 Tue Apr 21 05:18:40 UTC 2015 Ian Campbell <ijc@hellion.org.uk> jetson-tk1: Add PSCI configuration options and reserve secure code
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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