Searched hist:"2031 d6166a58623ae59034bc2353fcd2fabe9c30" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | el3_common_macros.S | 2031d6166a58623ae59034bc2353fcd2fabe9c30 Wed Jul 07 15:27:10 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(sys_reg_trace): initialize trap settings of trace system registers access
Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace system registers
accesses in lower ELs (EL2, EL1) in all security states when system
trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
and hence set it to zero to aligns with the Arm ARM reference
recommendation,that mentions software must writes RES0 bits with
all 0s.
Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| H A D | arch.h | 2031d6166a58623ae59034bc2353fcd2fabe9c30 Wed Jul 07 15:27:10 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(sys_reg_trace): initialize trap settings of trace system registers access
Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace system registers
accesses in lower ELs (EL2, EL1) in all security states when system
trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
and hence set it to zero to aligns with the Arm ARM reference
recommendation,that mentions software must writes RES0 bits with
all 0s.
Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | el3_common_macros.S | 2031d6166a58623ae59034bc2353fcd2fabe9c30 Wed Jul 07 15:27:10 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(sys_reg_trace): initialize trap settings of trace system registers access
Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace system registers
accesses in lower ELs (EL2, EL1) in all security states when system
trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
and hence set it to zero to aligns with the Arm ARM reference
recommendation,that mentions software must writes RES0 bits with
all 0s.
Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|
| H A D | arch.h | 2031d6166a58623ae59034bc2353fcd2fabe9c30 Wed Jul 07 15:27:10 UTC 2021 Manish V Badarkhe <Manish.Badarkhe@arm.com> feat(sys_reg_trace): initialize trap settings of trace system registers access
Trap bits of trace system registers access are in architecturally
UNKNOWN state at boot hence
1. Initialized trap bits to one to prohibit trace system registers
accesses in lower ELs (EL2, EL1) in all security states when system
trace registers are implemented.
2. These bits are RES0 in the absence of system trace register support
and hence set it to zero to aligns with the Arm ARM reference
recommendation,that mentions software must writes RES0 bits with
all 0s.
Change-Id: I4b6c15cda882325273492895d72568b29de89ca3
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
|